Very Large Scale Integration (VLSI) circuits are designed with the use of Electronic Design Automation (EDA) tools, also called Computer Aided Design (CAD) tools. Typically, the design process begins with a circuit being specified in a Hardware Description Language (HDL), such as Verilog or VHDL. The HDL description is a set of statements in a computer language format that define the functional operation to be performed by the circuit.
An HDL circuit simulator is used to run a circuit simulation of the HDL description. Modifications to the HDL description are made based upon the results of the HDL circuit simulation.
In addition to its function as a simulator of an HDL description, the HDL circuit simulator is used to generate a netlist. A netlist defines the components and interconnections between the components required to implement the functional operation specified in the HDL circuit description.
Once a netlist has been generated, there are a number of commercially available "silicon compilers", also called "place and route tools", that are used to convert the netlist into a semiconductor circuit layout. The semiconductor circuit layout specifies the physical implementation of the circuit in silicon, or some other semiconductive material.
A semiconductor circuit layout can be divided into different functional regions. Large dedicated functions are typically assigned to a functional region of a circuit. Smaller tasks that are not associated with large dedicated functions are typically implemented in an area of a semiconductor called a random logic region. The random logic region uses a selection of standard cell logic gates. Examples of standard cells include NAND gates, flip-flops, and multiplexers. They are called standard cells because, when implemented in silicon, each cell has a standard height. This allows the cells to be aligned with one another to form standard cell tracks. Signal routing tracks are then positioned between standard cell tracks. Metal connections between the routing tracks and standard cells allows specified logic to be executed by the standard cells of the standard cell tracks.
After a circuit has been placed and routed, a number of known techniques are used to verify the performance of the semiconductor circuit. The verification techniques may identify problems in the performance of the semiconductor circuit. In the case of the standard cell region (typically the random logic region of the semiconductor circuit), these problems are solved by placing additional standard cells at the ends of the standard cell tracks. The additional standard cells can then be connected to other standard cells to correct any problems.
The problem with this technique is that signal traces between the added standard cells and the original standard cells can be long, since the added standard cells are at the end of a standard cell track. The long signal traces result in capacitance problems in the signal paths of the semiconductor circuit. Another problem with this technique is that the place and route tool may have a difficult time even establishing a suitable signal trace between the added standard cells and the original standard cells.